The explosive growth of artificial intelligence and its movement to the edge and end devices have prompted significant research on highly energy efficient and low-latency non-von Neumann computing paradigms such as in-memory computing (IMC).
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Answer brought by NeuroSoC
The overarching objective of NeuroSoC is to develop a flexible computing system where an analog IMC-based neural processing unit is integrated into a multi-processor functional safe and secure system-on-chip to tackle the requirements of a wide set of edge-AI applications.
The NeuroSoC approach relying on a solid, mature, and qualified reliable Phase Change Memory technology, will enable to create an industrially proven path to go past the state of the art, answering to the level of maturity need which is compatible with a mass volume production and cost.
A hybrid In Memory Neural Processing Unit (IMNPU) based processor can target industrial, automotive, consumer, robotics, personal health, imaging but also scale up to servers/cloud, autonomous driving, NLP, advanced imaging/video, intrusion detection, etc.
The NeuroSoC architecture is expected to enhance the energy efficiency and compute density (TOPS/W/mm2) by more than 100x when compared to conventional general-purpose systems.
Specifically, NeuroSoC’s aim is to develop an advanced Multi-Processor System on Chip (MPSoC) prototype in FD-SOI 28nm CMOS technology that integrates:
- An AIMC IMNPU unit,
- A local digital processing subsystem,
- Functional safe multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor implementation,
- While covering IMNPU security aspects holistically to tackle the requirements of a wide set of edge-AI applications.