In Memory Computing approaches

Memory centric architectures can
be associated to many topologies​


Two broad classifications of IMC apply: DIMC (Digital In Memory Compute) and AIMC (Analog In memory Compute)​

In the case of DIMC the computation happens in the memory spread across the single memory bit cell and a group of bit cells that can be accessed in parallel to perform an accumulation operation. This deterministically generates a precise bit accurate output. ​

The AIMC architectures are associated to cases where the computation happens by way of an analog operation such as a current summation or charge transfer either in a column wise or a row wise fashion with an analog and digital conversion at the end to generate the final output​
In NeuroSoC the focus will be on AIMC​.


Detailed technical objectives

  • Design of a PCM computational memory tile for AIMC in 28nm FD-SOI technology
  • Design of a SRAM computational memory tile for AIMC in 28nm FD-SOI technology complementing the PCM one for selected ultra-low cost and always on use-cases
  • Design of a reusable and modular hybrid IMC based neural processing unit for scalable edge-AI SoCs
  • Assessment and characterization of security exploits techniques for IMC based NPUs
  • Enhancement of a RISC-V multicore microcontroller implementation to support functional safety
  • Explore functional safety solutions for IMNPU IPs for industrial and automotive use cases
  • Study and optimize AI Deep Learning algorithms optimized for IMC and selected use-cases
  • Prototype IMC based AI tools and compilers for efficient mapping of deep learning algorithms
  • Design of an advanced 28nm FD-SOI complete MPSoC integrating the technology developed in the project
  • Validate use-cases to assess the benefits of the technology and tools developed in the project